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| EM78M680 usb full speed microcontroller product specification d oc . v ersion 1.1 elan microelectronics corp. february 2007
trademark acknowledgments: ibm is a registered trademark a nd ps/2 is a trademark of ibm. windows is a trademark of microsoft corporation. elan and elan logo are trademarks of elan mi croelectronics corporation. copyright ? 2006 by elan microelectronics corporation all rights reserved printed in taiwan the contents of this specification are subject to change without further notice. elan microelectronics assumes no responsibility concerning the accuracy, ad equacy, or completeness of this sp ecification. elan microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. such information and material may change to conform to each confirmed order. in no event shall elan microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. elan microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. the software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordan ce with the terms of such agreement. elan microelectronics products are not intended for use in life support appliances, devices, or systems. use of elan microelectronics product in such applications is not supported and is prohibited. no part of this specification may be re produced or transmitted in any form or by any means without the expressed written permission of elan microelectronics. elan microelectronics corporation headquarters: no. 12, innovation road 1 hsinchu science park hsinchu, taiwan 30077 tel : +886 3 563-9977 fax : +886 3 563-9966 http : //www.emc.com.tw hong kong: elan (hk) microelectronics corporation, ltd. flat a, 19f., world tech centre 95 how ming street, kwun tong kowloon , hong kong tel : +852 2723-3376 fax : +852 2723-7780 elanhk@emc.com.hk usa: elan information technology group (usa) 1821 saratoga ave., suite 250 saratoga, ca 95070 usa tel : +1 408 366-8225 fax : +1 408 366-8220 europe: elan microelectronics corp. (europe) siewerdtstrasse 105 8050 zurich, switzerland tel : +41 43 299-4060 fax : +41 43 299-4079 http : //www.elan-europe.com shenzhen: elan microelectronics shenzhen, ltd. ssmec bldg., 3f, gaoxin s. ave. shenzhen hi-tech industrial park shenzhen, guandong, china tel : +86 755 2601-0565 fax : +86 755 2601-0500 shanghai: elan microelectronics shanghai, ltd. 23/bldg. #115 lane 572, bibo roa d zhangjiang hi-tech park shanghai, china tel : +86 21 5080-3866 fax : +86 21 5080-4600 contents product specification (v1.11) 02.10.2007 ? iii contents 1 general description .................................................................................................. 1 2 features ..................................................................................................................... 1 3 pin assignment ......................................................................................................... 4 3.1 function type description .................................................................................. 4 3.2 pin configuration................................................................................................ 4 4 pin description.......................................................................................................... 6 5 block diagram ........................................................................................................... 7 6 function description ................................................................................................ 7 6.1 program memory................................................................................................ 7 6.2 data memory ...................................................................................................... 8 6.2.1 operational regist ers........................................................................................10 6.2.1.1 r0 (indirect address regi ster) ........................................................... 10 6.2.1.2 r1 (timer/clo ck counter , tcc) ......................................................... 10 6.2.1.3 r2 (program counter & stack)........................................................... 10 6.2.1.4 r3 (statu s register) ........................................................................... 11 6.2.1.5 r4 (ram se lect register) .................................................................. 12 6.2.1.6 r5 (port 5 i/o regist er)...................................................................... 13 6.2.1.7 r6 (port 6 i/o regist er)...................................................................... 13 6.2.1.8 r7 (port 7 i/o regist er)...................................................................... 13 6.2.1.9 r8 (port 8 i/o regist er)...................................................................... 13 6.2.1.10 r9 (port 9 i/o regi ster)...................................................................... 13 6.2.1.11 ra (usb endpoint 0 status register) ................................................ 13 6.2.1.12 rc (fifo indire ct index r egister )...................................................... 14 6.2.1.13 rd (fifo indire ct data register) ....................................................... 14 6.2.1.14 re (interrupt status r egister) ............................................................ 15 6.2.1.15 rf (i nterrupt status register) ............................................................ 15 6.2.1.16 r10 (usb endpoint status r egister) ................................................. 15 6.2.1.17 r11 (ad controlle r/ad selection pin) ................................................ 16 6.2.1.18 r12 (dua l mode cont rol).................................................................... 17 6.2.1.19 r14 (adc output data) : a dc output data for selecting pin ........... 17 6.2.1.20 r17 (eeprom control regi ster) ....................................................... 18 6.2.1.21 r18~r1f (general purpose r egister ) ............................................... 18 6.2.1.22 r20~r3f (general purpose r egister) ............................................... 18 6.3 special function registers............................................................................... 19 6.3.1 a (accum ulator ).................................................................................................19 6.3.2 cont (contro l register)...................................................................................19 6.3.3 ioc5 ~ ioc9 (i/o po rt control r egister) ..........................................................20 6.3.4 ioca (rfcnt: rf control register).................................................................20 6.3.5 iocb (pwm_cnt : pwm cont roller) .................................................................20 contents ? product specification (v1.11) 02.10.2007 iv 6.3.6 iocc (r eserve).................................................................................................21 6.3.7 iocd (port 9 pull hi gh control r egister)..........................................................21 6.3.8 ioce (mcu cont rol regist er)...........................................................................21 6.3.9 iocf (interrupt mask register).........................................................................22 6.4 usb device controller ..................................................................................... 23 6.5 device address and endpoints......................................................................... 23 6.6 reset ................................................................................................................ 23 6.6.1 power-o n reset.................................................................................................23 6.6.2 watchdo g reset ................................................................................................23 6.6.3 usb reset.........................................................................................................24 6.7 saving power mode ......................................................................................... 24 6.7.1 power do wn m ode ............................................................................................24 6.7.2 dual cl ock mode ...............................................................................................24 6.8 interrupt ............................................................................................................ 25 6.9 pattern detect application (pda) ..................................................................... 26 6.9.1 function description..........................................................................................26 6.9.2 control register ................................................................................................26 6.9.2.1 iocf [2~3] pda enable contro l bit t ................................................. 26 6.9.2.2 ioca (pda c ontrol regi ster) ............................................................. 26 6.9.2.3 r15 eram1 (p.92 low pattern counter)........................................... 26 6.9.2.4 r16 eram1 (p.92 hi gh pattern counter).......................................... 26 6.9.2.5 r17 eram1 (p.93 low pattern counter)........................................... 26 6.9.2.6 r18 eram1 (p.93 hi gh pattern counter).......................................... 27 6.9.3 sampling rate and debounce length ..............................................................27 6.10 pulse width modulation (pwm) ....................................................................... 28 6.10.1 function description..........................................................................................28 6.10.2 duty cycle .........................................................................................................29 6.10.3 control register ................................................................................................29 6.10.3.1 r15 (pwm1 duty cycle regi ster) ...................................................... 29 6.10.3.2 r16 (pwm2 duty cycle regi ster) ...................................................... 29 6.10.3.3 iocb (pwm c ontrol regi ster)............................................................ 29 6.11 analog-to-digital converter (adc) .................................................................. 30 6.11.1 function description..........................................................................................30 6.11.2 contro l register ................................................................................................30 6.11.2.1 r11 (ad channel select regi ster)..................................................... 30 6.11.2.2 r13 (ad lsb data regi ster).............................................................. 31 6.11.2.3 r14 (ad msb data regi ster)............................................................. 31 7 absolute maximum ratings ................................................................................... 31 8 dc electrical characteristic ................................................................................... 32 contents product specification (v1.11) 02.10.2007 ? v appendix a special registers map ............................................................................................ 34 b instruction set ......................................................................................................... 41 c code option............................................................................................................. 44 d application circuit???????????????????????????..47 contents ? product specification (v1.11) 02.10.2007 vi specification revision history doc. version revision description date 0.9 preliminary version 2006/08/29 contents product specification (v1.11) 02.10.2007 ? 1 1 general description the EM78M680 is a series of 8-bit univ ersal serial bus, risc architecture, multi-time programming (mtp) microcontrollers. it is specifically designed for usb full speed device application. the EM78M680 also supports one device address and five endpoints. the EM78M680 has eight-level stack and four sets of interrupt sources. it has a maximum of 36 general input/output pins with the capacity of sinking large current. each device has 271 bytes of general purpose sram, 6k bytes of program rom, and is embedded with 32 bytes of eeprom. these series of ics have special features that meet user?s requirements. such features are: ? dual clock mode which allows the device to run on very low power. ? pattern detect application function which is used in serial transmission to count waveform width ? pulse width modulation that can generate a duty-cycle-programmable signal ? 24-channel ad converter with up to 10 bits resolution 2 features ? operating voltage: 4.4v ~ 5.25v ? usb specification compliance ? universal serial bus specification version 1.1 ? usb device class definition for human interface device (hid), firmware specification version 1.1 ? supports one device address and five endpoints ? usb application ? p74 (d+) has an internal pull-high resistor (1.5k ? ) ? usb protocol handling ? usb device state handling ? identifies and decodes standard usb commands to endpoint zero contents ? product specification (v1.11) 02.10.2007 2 ? built-in 8-bit risc mcu ? 8-level stacks for subroutine nesting, and interrupt ? 4 sets of interrupts ? 8-bit real time clock/counter (tcc) with overflow interrupt ? built-in rc oscillator free running for watchdog timer and dual clock mode ? two independent programmable prescalers for wdt and tcc ? two methods of power saving: ? power-down mode (sleep mode) ? dual clock mode ? two clocks per instruction cycle ? multi-time programmable ? set 1 int : (jump to 0x08) ? tcc overflow interrupt ? ep0 command in interrupt ? usb suspend interrupt ? usb reset interrupt ? usb host resume interrupt ? set 2 int : (jump to 0x10) ? rf1 low pattern interrupt ? rf1 high pattern interrupt ? rf2 low pattern interrupt ? rf2 high pattern interrupt ? set 3 int : (jump to 0x18) ? p77 port change interrupt ? p76 port change interrupt ? set 4 int : (jump to 0x20) ? ep1~5 output endpoint received o.k interrupt ? i/o ports ? 3 led sink pins ? each gpio pin in ports 5, 6, 8, p90~p93, p95, p96, p70~p72 and p76~p77, has an internal programmable pull-high resistor (25 k ? ) ? each gpio pin of port 6, p76~p77, and port 9 can wakeup the mcu from sleep mode by input state change contents product specification (v1.11) 02.10.2007 ? 3 ? internal memory ? built-in 6k 13 bits program rom ? built-in 271 bytes general purpose registers (sram) ? built-in usb application fifos ? built-in 32 bytes e 2 prom ? operation frequency ? normal mode: mcu runs on an external oscillator frequency of 4mhz, internal system frequency of 8mhz, 16mhz or 24mhz ? dual clock mode: mcu runs at a frequency of 256khz (or 32khz, 4khz, 500hz), using an internal oscillator with an external crystal resonator turned off to save power ? built-in pattern detecting applicati on for serial signal transmission ? built-in pulse width modulation (pwm) ? 2 channels pwm function on p.92 (pwm1) and p.93 (pwm2) ? 8-bit resolution of pwm output ? 8 selections of duty cycles ? built-in 24-channel analog-to-digital converter (adc) ? built-in ad converter with 10-bit resolution ? 4 types of adc clock source selection: 256k/128k/64k/32k ? built-in 3.3v voltage regulator ? for udc power supply ? pull-up source for the external usb resistor on d+ pin ? package type ? 44-pin qfp (EM78M680 (a/d) aq) ? 40-pin dip 600mil (EM78M680 (a/d) ap) ? 24-pin dip 600mil (e m78m680 (a/d) cp) ? 24-pin sop 300mil (EM78M680 (a/d) cm) ? 20-pin dip 300mil (EM78M680 (a/d) bp) ? 20-pin sop 300mil (EM78M680 (a/d) bm) contents ? product specification (v1.11) 02.10.2007 4 3 pin assignment 3.1 function type description the EM78M680 series has four types of packaging. each type is divided into two modules, namely; original, and with both e 2 prom and a/d converter. hence, packaging configuration for each series is defined. table 3.1 below summarizes which series of the EM78M680 belong to which module. table 3-1 packaging summary of EM78M680 series ic original with both EM78M680a EM78M680d 3.2 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p56 p57 p60 p61 p62 p63 p77 vdd osci osco vss v3.3 d+ d- p92/se1/pwm1 p93/se2/pwm2 p94/vpp vnn p54 p55 fig. 3-1 EM78M680*bp/*bm (20-pin dip/sop) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 19 20 21 22 23 24 osco vss v3.3 d+ d- p92/se1/pwm1 p93/se2/pwm2 p94/vpp vnn p54 p61 p62 p63 p64 p65 p66 p77 p76 vdd osci 15 16 17 18 p55 p56 p60 p57 fig. 3-2 EM78M680*cp/*cm (24-pin dip/sop) contents product specification (v1.11) 02.10.2007 ? 5 1 2 3 4 5 6 7 8 9 10 11 12 29 30 35 36 37 38 39 40 vss v3.3 d+ d- p90 p91 p92/se1/pwm1 p93/se2/pwm2 p94/vpp vnn p64 p65 p66 p67 p72 p71 p70 vdd osci osco 31 32 33 34 p50 p51 p63 p62 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 p52 p53 p54 p55 p56 p57 p80 p81 p61 p60 p87 p86 p85 p84 p83 p82 fig. 3-3 EM78M680*ap (40-pin dip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 44 43 p91 p92/se1/pwm1 p93/se2/pwm2 p94/vpp p95 p96 vnn p50 p51 p52 p53 p87 p60 p61 p62 p63 p64 p65 p66 p67 p72 p71 p54 p55 p56 p57 p80 p81 p82 p83 p84 p85 p86 p90 d- d+ v3.3 vss osco osci vdd p76 p77 p70 contents ? product specification (v1.11) 02.10.2007 6 fig. 3-4 EM78M680*aq (44-pin qfp) 4 pin description symbol i/o function p50 ~ p57 i/o general 8-bit bidirectional input/output port. all pins on this port can be internally pulled-high by register ioce bit 0. all port 5 input/output pins can be used for adc function. p60 ~ p67 i/o general 8-bit bidirectional input/output port. all pins on this port can be internally pulled-high by register ioce bit 1. all port 6 input/output pins can be used for adc function. p70 ~ p72 p76 ~ p77 i/o general 8-bit bidirectional input/output port. all pins on this port can be internally pulled-high by register ioce bit 3. the sink current of p70 ~ p7 2 are used for driving led. p80 ~ p87 i/o general 8-bit bidirectional input/output port. all pins on this port can be internally pulled-high by register ioce bit 2. all port 8 input/output pins can be used for adc function. p94 / vpp i mtp program pin. used in programming the on-chip rom. p94 functions as an input pin only (without an internally pulled-high resistor). p90 ~ p93 p95 ~ p96 i/o general bidirectional input/outpu port. each pin can be internally pulled-high by register iocd. p92 ~ p93 can be used for pwm (pulse width modulation) or pda (serial signal transmission application) function. usb d+ i/o usb d+ pin. built-in intern al 1.5k pulled-high resistor to v3.3 usb d- i/o usb d- pin. osci i 4mhz crystal resonator input. osco i/o return path for 4mhz crystal resonator. vnn ? mtp program pin. used in programmi ng the on-chip rom. during normal operation, this pin is connected to ground. v3.3 o 3.3v dc voltage output from an internal re gulator. this pin has to be tied to a 4.7sf capacitor. vdd ? connect to the usb power source or to a nominal 5v-power supply. actual vdd range can vary between 4.4v and 5.25v. vss ? connect to ground. contents product specification (v1.11) 02.10.2007 ? 7 5 block diagram oscillator timing control built-in rc prescaler r1 (tcc) wdt timer data & control bus osci osco r2 (pc) stack1 alu acc r3 (status) rom instruction register instruction decoder interrupt control reset & sleep & wake up control 3.3v regulator usb device controller vdd v3.3 transceiver d+ d- tcc wdt ram r4 (rsr) stack2 stack3 stack4 stack5 rc,rd prescaler i/o port 8 p80/ad p81/ad p82/ad p83/ad p84/ad p85/ad p86/ad p87/ad i/o port 9 p90 p91 p92/pwm1/se1 p94/vpp p95 p96 i/o port 7 pattern detect application adc pwm stack6 stack7 p70 p71 p72 p93/pwm2/se2 i/o port 6 p60/ad p61/ad p62/ad p63/ad p64/ad p65/ad p66/ad p67/ad i/o port 5 p50/ad p51/ad p52/ad p53/ad p54/ad p55/ad p56/ad p57/ad p76 p77 stack8 ep fifo eeprom 6 function description the EM78M680 memory is organized into four spaces, namely; user program memory in 6k 13 bits rom space, data memory in 271 bytes sram space, eeprom space, and usb application fifos for endpoint 0, endpoint 1, endpoint 2, endpoint 3, endpoint 4, endpoint 5. furthermore, several registers are used for special purposes. 6.1 program memory the program space of the EM78M680 is 6k bytes, and is divided into six pages. each page is 1k bytes long. after a reset, the 13-bit program counter (pc) points to location zero of the program space. the interrupt vectors are at 0x0008 (usb and tcc interrupts), 0x0010 (rf interrupt), 0x0018 (p76 p77 port change interrupt) and 0x020 (ep1~5 output endpoint interrupt). contents ? product specification (v1.11) 02.10.2007 8 after an interrupt, the mcu will auto pu sh the ram bank value (rsr bits 6, 7) (ra,7), page selector (status bits 5, 6, 7), and accumulator (a) and fetch the next instruction from the corresponding addres s as illustrated in the following diagram. after reset address 0x0000 reset vector 0x0008 0x0010 0x0018 0x0020 0x03ff first set of interrupt vector second set of interrupt vector third set of interrupt vector fourth set of interrupt vector page 0 0x0400 0x07ff page 1 0x0800 0x0bff page 2 0x0c00 0x0fff page 3 0x1000 0x13ff page 4 0x1400 0x17ff page 5 fig 6-1 EM78M680 data ram organization 6.2 data memory the data memory has 271 bytes sram space. it is also equipped with usb application fifo space for usb application. figure 6.2 shows the organization of the data memory space. pc contents product specification (v1.11) 02.10.2007 ? 9 " # $ % & ' 3 3 5 $ $ 3 1 $ 3 4 u b u v t 3 3 4 3 3 1 p s u 3 1 p s u 1 1 p s u 3 1 p s u 3 1 p s u 3 " & 1 t u b u v t 3 & & 1 3 @ $ / 5 3 $ ' * ' 0 j o e f y 3 % ' * ' 0 e b u b 3 & * 4 3 3 ' * 4 3 * 0 $ % 1 1 v m m i j h i * 0 $ & . $ 6 $ 3 * 0 $ ' * / 5 . " 4 , 4 u b d l m f w f m t * 0 $ * 0 $ * 0 $ * 0 $ * 0 $ y # b o l 3 f h j t u f s # b o l y # b o l 3 f h j t u f s # b o l y # b o l 3 f h j t u f s # b o l y # b o l 3 f h j t u f s # b o l ' ' y # b o l 3 f h j t u f s # b o l y # b o l 3 f h j t u f s # b o l y # b o l 3 f h j t u f s # b o l y # b o l 3 f h j t u f s # b o l * 0 $ " 3 ' $ / 5 3 3 f t f s w f e 3 3 f t f s w f e 3 3 f t f s w f e 3 5 . 3 * 0 $ # 1 8 . @ $ / 5 3 " % $ 3 " % @ 4 f m 3 " % @ - 4 # 3 " % @ . 4 # 3 " % @ 3 b u f & y u s b 3 " . & y u s b 3 " . 3 4 & @ - 0 8 3 4 & @ ) * ( ) 3 4 & @ - 0 8 3 4 & @ ) * ( ) 3 3 & 1 4 u b u v t s f h & o e q p j o u 0 6 5 e b u b & o e q p j o u * / e b u b & o e q p j o u e b u b & o e q p j o u e b u b & o e q p j o u e b u b & o e q p j o u e b u b & o e q p j o u e b u b 3 f t f s w f e 3 f t f s w f e & & 1 3 0 . e b u b " d d v n v m b u p s 3 1 8 . q s f t f u 3 1 8 . q s f t f u 3 # 3 $ 3 % 3 & 3 ' 3 3 " 3 # 3 $ 3 % 3 & 3 ' 3 " 3 # ( f o f s b m s f h j t u f s 3 4 3 3 f t f s w f e * 0 $ $ 3 f t f s w f e fig. 6-2 data memory configuration contents ? product specification (v1.11) 02.10.2007 10 6.2.1 operational registers 6.2.1.1 r0 (indirect address register) r0 is not a physically implemented register. it is used as an indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). 6.2.1.2 r1 (timer/clock counter, tcc) this register tcc, is an 8-bit timer or counter. it is incremented by the instruction cycle clock, and is readable and writable as any other register. 6.2.1.3 r2 (program counter & stack) ? r2 and the hardware stacks are 13 bits wide. ? the structure is depicted in fig. 3. ? generates 6k 13 on-chip rom addresses to the relative programming instruction codes. one program page is 1024 words long. ? all the r2 bits are set to "0"s when a reset condition occurs. ? "jmp" instruction allows direct loading of the lower 10 program counter bits. thus, "jmp" allows jump to any location on one page. ? "call" instruction loads the lower 10 bits of the pc, and then pc+1 is pushed onto the stack. thus, the subroutine entry address can be located anywhere within a page ? "ret" ("retl k", "reti") instruction loads the program counter with the contents at the top of stack. ? "mov r2, a" allows the loading of an address from the "a" register to the lower 8 bits of pc, and the ninth and tenth bits (a8~a9) of pc are cleared. ? "add r2, a" allows a relative address to be added to the current pc, and the ninth and tenth bits of pc are cleared. ? any instruction that is written to r2 (e.g. "add r2, a", "mov r2, a", "bc r2,6",etc ? ), except "tbl" will cause the ninth and tenth bits (a8~a9) of the pc to be cleared. thus, the computed jump is limited to the first 256 locations of any program page. ? "tbl" allows a relative address to be added to the current pc (r2+a r2), and contents of the ninth and tenth bits (a8~a9) of the pc are not changed. thus, the computed jump can be on the second (third, or 4th) 256 locations on one program page. ? for the EM78M680, the most significant bits (a10~a12) will be loaded with the contents of bits ps0~ps2 in the status register (r3) upon the execution of a "jmp", "call", or any other instructions which writes to r2. contents product specification (v1.11) 02.10.2007 ? 11 ? all instructions are single instruction cycle except for the instruction that would change the contents r2. such instruction will need one more instruction cycle. pc a12~a10 a9~a8 a7 ~ a0 call ret retl reti 0000 03ff page 0 000 0400 07ff page 1 0800 0bff page 2 0c00 0fff page 3 001 010 011 0008:ram module 0 interrupt interrupt location 0010:ram module 1 interrupt 0000:reset location 1000 13ff 1400 17ff page 4 page 5 100 101 stack 1 stack 7 stack 6 stack 5 stack 4 stack 3 stack 2 stack 8 0018:ram module 2 interrupt 0020:ram module 3 interrupt 6.2.1.4 r3 (status register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ps2 ps1 ps0 t p z dc c after an interrupt occurs, mcu will save r3 bit5~7 first and clear ps0~ps2 automatically. r3 [0] carry flag r3 [1] auxiliary carry flag r3 [2] zero flag. it will be set to 1 when the result of an arithmetic or logic operation is zero. r3 [3] power down flag. it will be set to 1 during power-on phase or by ?wdtc? command and cleared when the mcu enters into power-down mode. it remains in its previous state after a watchdog reset. ? 0 ? : power-down mode ? 1 ? : power on values of rst, t and p after a reset reset type t p power on 1 1 wdt during operation mode 0 p wdt wake-up during sleep 1 mode 0 0 contents ? product specification (v1.11) 02.10.2007 12 wdt wake-up during sleep 2 mode 0 p wake-up on pin change during sleep 2 mode p p * p: previous value before reset status of rst, t and p being affected by events event t p power on 1 1 wdtc instruction 1 1 wdt time-out 0 * p slep instruction 1 0 wake-up on pin change during sleep 2 mode p p * p: previous value before reset r3 [4] time-out flag. it will be set to 1 during power-on phase or by ?wdtc? command. it is reset to 0 by wdt time-out. ? 0 ? : watchdog timer with overflow ? 1 ? : watchdog timer without overflow r3 [5~7] page selection bits. these three bits are used to select the page of the program memory. ps2 ps1 ps0 program memory page [address] 0 0 0 page 0 [000-3ff] 0 0 1 page 1 [400-7ff] 0 1 0 page 2 [800-bff] 0 1 1 page 3 [c00-fff] 1 0 0 page 4 [1000-13ff] 1 0 1 page 5 [1400-17ff] 6.2.1.5 r4 (ram select register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bk1 bk0 ad5 ad4 ad3 ad2 ad1 ad0 r4 (ram select register) contains the address of the registers. when interrupt occurs , the mcu will save r4 value automatically. r4 [0~5] are used to select registers (address: 0x00h~0x3fh) in indirect addressing mode. r4 [6~7] are used to determine which bank is activated among the 8 banks. to select a register bank, refer to the table below : r4[7]bk1 r4[6]bk0 ram bank # 0 0 0 1 bank 0 bank 1 contents product specification (v1.11) 02.10.2007 ? 13 1 1 0 1 bank 2 bank 3 6.2.1.6 r5 (port 5 i/o register) default value: (0b_0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p57 p56 p55 p54 p53 p52 p51 p50 6.2.1.7 r6 (port 6 i/o register) default value: (0b_0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p67 p66 p65 p64 p63 p62 p61 p60 6.2.1.8 r7 (port 7 i/o register) default value: (0b_0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p77 p76 d- d+ ? p72 p71 p70 6.2.1.9 r8 (port 8 i/o register) default value: (0b_0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p87 p86 p85 p84 p83 p82 p81 p80 6.2.1.10 r9 (port 9 i/o register) default value: (0b_0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? p96 p95 p94 p93 p92 p91 p90 6.2.1.11 ra (usb endpoint 0 status register): default value: (0b0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extr _r remote status ep0_w ep0_r dev _resume udc_suspend udc_writing stall ra [0] stall flag. when the mcu receives an unsupported command or invalid parameters from host, this bit will be set to 1 by the firmware to notify the udc to return a stall handshake. when a successful setup transaction is received, this bit is clea red automatically. this bit is both readable and writable. ra [1] udc writing flag. read only. when this bit is equal to ?1,? it indicates that the udc is writing da0ta into the ep0?s fifo or reading data from it. during this time, the firmware will avoid accessing the fifo until the udc finishes writing or reading. this bit is only readable. 1 : ep0?s fifo is busy 0 : ep0?s fifo is free for data transition. ack, nak are reset. ra [2] udc suspend flag. if this bit is equal to 1, it indicates that the usb bus has no traffic for a specified period of 3.0 ms. this bit will also be cleared automatically when a bus activity takes place. this bit is only readable. contents ? product specification (v1.11) 02.10.2007 14 ra [3] device resume flag. this bit is set by firmware to generate a signal to wake up the usb host and is cleared as soon as the usb suspend signal becomes low. this bit can only be set by firmware and cleared by hardware. it cam only be used under dual mode. this bit is both readable and writable. ra [4] ep0_r flag. this bit informs the udc to read the data written by the firmware from the fifo. then the udc will automatically send the data to the host. after the udc finishes reading the data from the fifo, this bit will be cleared automatically. therefore, before writing data into fifo, the firmware will first check this bit to avoid overwriting the data. this bit can only be set by the firmware and cleared by the hardware. ra [5] ep0_w. after the udc completes w riting data to the fifo, this bit will be set automatically. the firmware w ill clear it as soon as it gets the data from ep0?s fifo. only when this bit is cleared will the udc be able to write a new data into the fifo. therefore, before the firmware can write a data into the fifo, this bit must first be set by the firmware to prevent the udc from writing data at the same time. this bit is both readable and writable. ra [6] remote wake-up status. pass device remote wake-up setting from the pc. ra [7] extra ram switch. ram block switch 0: switch to bank 0~bank 3 and external ram0 1: switch to bank 4~bank 7 and external ram1 6.2.1.12 rc (fifo indirect index register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 uad4 uad3 uad2 uad1 uad0 rc [0~4] application fifo address registers. these five bits are the address pointer of application fifo. rc [5~7] undefined registers. 6.2.1.13 rd (fifo indirect data register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uad7 uad6 uad5 uad4 uad3 uad2 uad1 uad0 rd (application fifo data register) contains the data in the register of which address is pointed by rc. contents product specification (v1.11) 02.10.2007 ? 15 6.2.1.14 re (interrupt status register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p77_if p76_if reserved reserved rf2_high rf2_low rf1_high rf1_low re [0] rf1_low flag: pattern detectio n interruption flag. rf1 low pattern compare flag. re [1] rf1_high flag: pattern detectio n interruption flag. rf1 high pattern compare flag. re [2] rf2_low flag: pattern detectio n interruption flag. rf2 low pattern compare flag. re [3] rf2_high flag: pattern detect ion interruption flag. rf2 high pattern compare flag. re [4~5] reserved. do not use. re [6] p76_if: p76 state change interruption flag. re [7] p77_if: p77 state change interruption flag. the interrupt vector is in 0x0018 address. 6.2.1.15 rf (interrupt status register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 out ep_if ? ? resume_if usbreset_if suspend_if ep0_if tcc_if rf [0] tcc timer overflow interruption flag. it will be set while tcc timer overflows, and is cleared by the firmware. rf [1] endpoint zero interruption fl ag. it will be set when the EM78M680 receives vender /customer command to endpoint zero. this bit is cleared by the firmware rf [2] usb suspend interrupt flag: it will be set when the EM78M680 finds the usb suspend signal on usb bus. this bit is cleared by the firmware. rf [3] usb reset interrupt flag. it w ill be set when the host issues the usb reset signal. rf [4] usb host resume interrupt flag. it will be set only under dual clock mode when the usb suspend signal becomes low. rf [5~6] not used and read as ?0?. rf [7] out endpoint interrupt flag. it will be set when the fifo of outendpoint has been received data from host. extra ram0 : 6.2.1.16 r10 (usb endpoint status register) : default (0b0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ep5_st ep4_st ep3_st ep2_st ep1_st contents ? product specification (v1.11) 02.10.2007 16 r10 [0~4] epx_st: end point state flag. these five bits inform the udc to read the data written by the firmware from the fifo. then the udc will au tomatically send the data to the host. after udc finishes reading the data from the fifo, this bit will be automatically cleared. therefore, be fore writing data into fifo?s, the firmware will first check this bit to avoid overwriting the data. these five bits can only be set by the firmware and cleared by the hardware. readable and writable. for out endpoint: after an out token is finish, and the udc completes writing data to the fifo, this bit w ill be set automatica lly, and run into interrupt vector 0x0020. the firmware should clear it as soon as it gets the data from out endpoint?s fifo. only when this bit is cleared will the udc be able to write a new data into the fifo. 6.2.1.17 r11 (ad controller/ad selection pin) : default (0b0001_ 1111) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ad_start ad_r1 ad_r0 ad_a4 ad_a3 ad_a2 ad_a1 ad_a0 r11 [0~4] ad channel selector: if the ad number is from zero to 0x17, the ad converter will be powered on. otherwise, it will be powered off. ad number 00000 00001 00010 00011 ad pin ad0 ad1 ad2 ad3 ad number 00100 00101 00110 00111 ad pin ad4 ad5 ad6 ad7 ad number 01000 01001 01010 01011 ad pin ad8 ad9 ad10 ad11 ad number 01100 01101 01110 01111 ad pin ad12 ad13 ad14 ad15 ad number 10000 10001 10010 10011 ad pin ad16 ad17 ad18 ad19 ad number 10100 10101 10110 10111 ad pin ad20 ad21 ad22 ad23 r11 [5~6] ad conversion clock source. 00 : 256k 01 : 128k 10 : 64k 11 : 32k r11 [7] ad converter ready flag. 0 ? 1 : start ad conversion (set by firmware). 1 ? 0 : when ad finishes converting and has moved digital data into the ad data register, this bit will be reset by hardware. note contents product specification (v1.11) 02.10.2007 ? 17 hardware can enable this function only at the ad channel selector of the functional i/o port . after power-on reset, the initial value of this register is 0b0001 1111 . 6.2.1.18 r12 (dual mode control) : default (0b0000_1000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? usb_token low fr1 low fr0 /low freq ? ? ? r12 [3] /low freq: dual clock control bit. this bit is used to select the frequency of the system clock. when this bit is set to 0, the mcu will run on very slow frequency for power saving purposes and the udc will stop working. 0 : slow frequency (500hz~256khz) 1 : normal frequency r12 [4~5] low fr0 ~ low fr1: low frequency switches. these bits select the operation frequency in dual clock mode. four frequencies are available and can be chosen as dual clock mode for running the mcu program. low fr1 low fr0 frequency 0 0 500hz 0 1 4khz 1 0 32khz 1 1 256khz ? bit 6 (usb_token) : set when usb token from host. reset when end of the to k e n . 6.2.1.19 r14 (adc output data) : adc output data for selecting pin. default (0b0000_0000). read only when the a/d conversion is completed, the result is loaded to r13 & r14. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb1 adb0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 r15 : the high level time of the 1st pwm module that outputs to p92 (if pwm function is enabled). r16 : the high level time of the 2nd pwm module that outputs to p93(if pwm function is enabled). contents ? product specification (v1.11) 02.10.2007 18 r15~r16 can be a general purpose register if the pwm function is disabled. 6.2.1.20 r17 (eeprom control register) : default (0b0000_0011) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ee_act ee_reset ee_a4 ee_a3 ee_o.k ee_c1 ee_c0 this register is a general register if the eeprom function is disabled. r17 [0~1] ee_c0 ~ ee_c1: eeprom control bits. 00 : read data from eeprom to eeprom fifo. 01 : write data from eeprom fifo to eeprom 10 : erase eeprom 11 : disable eeprom function r17 [2] ee_o.k: eeprom activated o.k bits. 0 : not o.k 1 : o.k r17 [3~4] ee_a4 ~ ee_a3: bank selector. the eeprom is divided into four banks, these two bits can select which bank of the eeprom to read, write or erase. 00 : byte 0 ~byte 7 01 : byte8~byte 15 10 : byte16~byte 23 11 : byte 24~byte 31 r17 [ 5] ee_reset: eeprom fifo address reset flag. 0 : default. ee_reset is set to 0 after fifo address is reset 1 : reset eeprom fifo address by firmware r17 [ 6] ee_act: eeprom activated mode switch. 0 : activate all eeprom 1 : activate partial eeprom 6.2.1.21 r18~r1f (general purpose register) r17~r1f are general-purpose registers. 6.2.1.22 r20~r3f (general purpose register) r20~r3f (including banks 0~3) are general-purpose registers. extra ram1 : r10 ~ r14 (reserved register) : do not use contents product specification (v1.11) 02.10.2007 ? 19 r15 (se1_low ): low signal counter of the 1st rf module that inputted from p92. r16 (se1_high ): high signal counter of the 1st rf module that is inputted from p92. r17 (se2_low ): low signal counter of the 2nd rf module that is inputted from p93. r18 (se2_high ): low signal counter of the 2nd rf module that is inputted from p93. r15 ~ r18 are rf timing counter registers if rf function is enabled by setting bit 2 or bit 3 of iocf. otherwise, they are general registers. r19~r1f (general purpose register) r19~r1f are general-purpose registers. r20~r3f (general purpose register) r20~r3f (including banks 4~7) are general-purpose registers. 6.3 special function registers 6.3.1 a (accumulator) the accumulator is an 8-bit register that holds operands and results of arithmetic calculations. it is not addressable. after an interrupt occurs, the accumulator is auto-saved by hardware. 6.3.2 cont (control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? int tsr2 tsr1 tsr0 psr2 psr1 psr0 except for bit 6 (interrupt enable control bit), the cont register can be read by the instruction "contr" and written to by the instruction ?contw". cont [6] int: an interrupt enable flag cannot be written by the contw instruction. cont [3~5] tsr0 ~ tsr2: tcc prescaler bit cont [0~2] psr0 ~ psr2: wdt prescaler bits psr2 psr1 psr0 tcc rate (base freq: fosc/2) wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 contents ? product specification (v1.11) 02.10.2007 20 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 6.3.3 ioc5 ~ ioc9 port direction control register these are i/o port (port5 ~ port7) direction control registers. each bit controls the i/o direction of three i/o ports respective ly. when these bits are set to 1, the relative i/o pins become input pins. similarly, the i/o pins becomes outputs when the relative control bits are cleared. 0 : output direction 1 : input direction 6.3.4 ioca (rfcnt: rf control register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? rf2 rf1 rf0 rf_dbn2 rf_dbn1 rf_dbn0 ioca [0~2] rf_dbn0 ~ rf_dbn2: these are used for defining debounce times in rf pattern detecting application. ioca [3~5] rf0 ~ rf2: rf timing prescaler bits. base on mcu frequency. rf2 rf1 rf0 timing rate 8mhz system clock (time(cnt.)) 256khz rc mode (time (cnt.)) 0 0 0 1:1 0.125s (1), 31.875s (255) 3.91s (1), 996.1s (255) 0 0 1 1:2 0.25s (1), 63.75s (255) 7.81s (1), 1992s (255) 0 1 0 1:4 0.5s (1), 127.5s (255) 15.625s (1), 3984s (255) 0 1 1 1:8 1s (1), 255s (255) 31.25s (1), 7969s (255) 1 0 0 1:16 2s (1), 510s (255) 62.5s (1), 15.938ms (255) 1 0 1 1:32 4s (1), 1020s (255) 125s (1), 31.875ms (255) 1 1 0 1:64 8s (1), 2040s (255) 250s (1), 63.75ms (255) 1 1 1 1:128 16s (1), 4080s (255) 500s (1), 127.5ms (255) 6.3.5 iocb (pwm_cnt: pwm controller) : default (0b0000_0001) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw2_e pw1_e - - - pwm_sr2 pwm_sr1 pwm_sr0 iocb [0~2] pwm_sr0 ~ pwm_sr2: pwm clock prescaler base on mcu frequency (ex : fosc = 8mhz) pwm_sr2 pwm_sr1 pwm_sr0 clock (hz) 0 0 0 fosc / 2 0 0 1 fosc / 4 0 1 0 fosc / 8 0 1 1 fosc / 16 1 0 0 fosc / 32 1 0 1 fosc / 64 1 1 0 fosc / 128 contents product specification (v1.11) 02.10.2007 ? 21 1 1 1 fosc / 256 iocb [6] (pw1_e): pw1 enable. the 1st pwm (p92) module enable bit. 0 : disable the pwm function of the 1st module 1 : enable the pwm function of the 1st module iocb [7] (pw2_e): pwm2 enable: the 2nd pwm (p93) module enable bit. 0 : disable the pwm function of the 2nd module 1 : enable the pwm function of the 2nd module 6.3.6 iocc (reserve): do not use 6.3.7 iocd (port 9 pull high control register) default value: (0b_1111_1111) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 /ph96 /ph95 1 /ph93 /ph92 /ph91 /ph90 iocd [0~6] /ph90 ~ /ph96: these bits control the 25k ? pull-high resistor of individual pins in port 9. if the i/o port is set as output, the pull-high function is disabled. 0 : enable the pull-high function 1 : disable the pull-high function 6.3.8 ioce (mcu control register) : default (0b1101_1111) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s7 /wue wte slpc /pu7 /pu8 /pu6 /pu5 ioce [0~3] /pu5~/pu8: pull-high control register. default=1, disable pull high function. if the i/o port is set as ou tput, the pull-high function is disabled. 0 : enable the pull-high function 1 : disable the pull-high function ioce [4] slpc: this bit can be cleared by the firmware and set during power-on, or by the hardware at th e falling edge of wa ke-up signal. when this bit is cleared, the clock system is disabled and the mcu enters into power down mode. at the transition of wake-up signal from high to low, this bit is set to enable the clock system. 0 : sleep mode. the device is in power down mode. 1 : run mode. the device is working normally. ioce [5] wte: watchdog timer enable bit. wdt is disabled/ enabled by the wte bit. 0 : disable wdt 1 : enable wdt ioce [6] /wue: enable the weak-up function as triggered by port- changed. contents ? product specification (v1.11) 02.10.2007 22 0 : enable wake-up function 1 : disable wake-up function ioce [7] s7 bit : s7 defines the driving ability of p70-p72 0 : normal output 1 : enhance the driving ability of led 6.3.9 iocf (interrupt mask register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 outep_ie p76/p77_ie reserved resume_ie rf2_ie rf1_ie usb_ie tcc_ie iocf [0] tcc_ie: tcif interrupt enable bit 0 : disable tcif interrupt 1 : enable tcif interrupt iocf [1] usb_ie: usb interrupt enable bit. bits 1, 2, 3 of rf interrupt will be enabled while this bit is set. 0 : disable usb_ie interrupt 1 : enable usb_ie interrupt iocf [2] rf1_ie: rf1 pattern compare interrupt enable bit. bits 0, 1 of re interrupt will be enabled while this bit is set. 0 : disable rf1_ie interrupt 1 : enable rf1_ie interrupt iocf [3] rf2_ie: rf2 pattern compare interrupt enable bit. bits 2, 3 of re interrupt will be enabled while this bit is set. 0 : disable rf2_ie interrupt 1 : enable rf2_ie interrupt iocf [4] resume_ie: usb resume interrupt enable bit 0 : disable resume_ie interrupt 1 : enable resume_ie interrupt iocf [5] reserved. do not use . iocf [6] p76/77_ie: p76/p77 port change interrupt enable bit. bits 6, 7 of re interrupt will be enabled while this bit is set. 0 : disable p76/p77_ie interrupt 1 : enable p76/p77_ie interrupt iocf [7] outep_ie: output endpoint interrupt enable bit 0 : disable outep_ie interrupt 1 : enable outep_ie interrupt contents product specification (v1.11) 02.10.2007 ? 23 only when the global interrupt is enabled by the eni instruction that the individual interrupt will work. after disi instruction, any interrupt will not work even if the respective control bits of iocf are set to 1. the usb host resume interrupt works only under dual clock mode. this is because when the mcu is under sleep mode, it will be waked up by the udc resume signal automatically 6.4 usb device controller the usb device controller (udc) built-in in the EM78M680 can interpret the usb standard command and response automati cally without involving firmware. the embedded series interface engine (sie) handles the serialization and de-serialization of actual usb transmission. thus, a developer can concentrate his efforts more in perfecting the device actual functions and spend less energy in dealing with usb transaction. the udc handles and decodes most standard usb commands defined in the usb specification rev 1.1. if the udc receives an unsupported command, it will set a flag to notify the mcu the receipt of such command. each time the udc receives a usb command, it writes the command into ep0?s fifo . only when it receives unsupported command that the udc will notify the mcu through interrupt . therefore, the EM78M680 is very flexible for usb applications since developers can freely choose the method of decoding the usb command as dictated by different situation. 6.5 device address and endpoints the EM78M680 supports one device address and five endpoints, ep0 for control endpoint, ep1 ~ ep5 for interrupt/bulk /isochronous endpoints . sending data to usb host in EM78M680 is very easy. just write data into the ep?s fifo, then set the flag, and the udc will handle the rest. it will then confirm that the usb host has received the correct data from the EM78M680. 6.6 reset the EM78M680 provides three types of reset: (1) power-on reset, (2) watchdog reset, and (3) usb reset. 6.6.1 power-on reset power-on reset occurs when the device is attached to power and a reset signal is initiated . the signal will last until the mcu becomes stable . after a power-on reset, the mcu enters the following predetermined states (see below), and then, it is ready to execute the program . a. the program counter is cleared . b. the tcc timer and watchdog timer are cleared . contents ? product specification (v1.11) 02.10.2007 24 c. special registers and special control registers are all set to their initial value . 6.6.2 watchdog reset when the watchdog timer overflows, it causes the watchdog to reset . after it resets, the program is executed from the beginning and some registers will be reset . the udc however, remains unaffected . 6.6.3 usb reset when the udc detects a usb reset signal on the usb bus, it interrupts the mcu, then proceeds to perform the specified process that follows . after a usb device is attached to the usb port, it cannot respond to any bus transactions until it receives a usb reset signal from the bus . 6.7 saving power mode the EM78M680 provides two options of power-saving modes for energy conservation, i.e., power down mode and dual clock mode . 6.7.1 power down mode the EM78M680 enters into power down mode by clearing the slpc register (ioce[4]) . during this mode, the oscillator is turned off and the mcu goes to sleep . it will wake up when signal from usb host is resumed, or when the watchdog reset or the input port state changes . if the mcu wakes up when the i/o port st atus changes, the direction of i/o port should be set at input direction, then read the port status . for example: : // set the port 6 to input port mov a , 0xff iow port6 // read the status of port 6 mov port6, port6 // clear the run bit ior 0xe and a , 0b11101111 iow 0xe : : if the mcu is awaken by a usb resume signal, the next instruction will be executed and one flag, ioce[4] will be set to 1 . 6.7.2 dual clock mode the EM78M680 has one internal osc illator for power saving application . clearing the bit r12 [3] of exteraram0 will enable the low fr equency oscillator . at the contents product specification (v1.11) 02.10.2007 ? 25 same time, the external oscillator will be turned off . then the mcu will run under very low frequency to conserve power . four types of frequency are available for selection in setting bits r12 [4, 5] . the usb host resume interrupt can only be used in this mode . if this interrupt is enabled, the mcu will be interrupted when the usb resume signal is detected on usb bus . 6.8 interrupt the em78680 has four interrupt vectors 0x0008, 0x0010, 0x0018, 0x0020. when an interrupt occurs during an mcu running program, it will jump to the interrupt vector and execute the instructions sequentially from the interrupt vector. re and rf is the interrupt status register, which re cords the interrupt status in the relative flags/bits. the interrupt condition could be one of the following: ? set 1 int: (jump to 0x08) ? tcc overflow interrupt ? ep0 command in interrupt ? usb suspend interrupt ? usb reset interrupt ? usb host resume interrupt ? set 2 int: (jump to 0x10) ? rf1 low pattern interrupt ? rf1 high pattern interrupt ? rf2 low pattern interrupt ? rf2 high pattern interrupt ? set 3 int: (jump to 0x18) ? p77 port change interrupt ? p76 port change interrupt ? set 4 int: (jump to 0x20) ? ep5~8 output endpoint received o.k interrupt iocf is an interrupt mask register which can be set bit by bit. while their respective bit is written to 0, the hardware interrupt will inhibit, that is, the EM78M680 will not jump to the interrupt vector to execute instructions. but the interrupt status flags still records the cond itions no matter whether the interrupt is contents ? product specification (v1.11) 02.10.2007 26 masked or not. the interrupt status flags must be cleared by firmware before leaving the interrupt service ro utine and enabling interrupt. the global interrupt is enabled by the eni (reti) instruction and is disabled by the disi instruction. 6.9 pattern detect application (pda) 6.9.1 function description this function is designed for the serial signal transmission, e.g., the transmission between a wireless device and its receiver box. the EM78M680 has two sets of built-in pattern detect application block that ensures the EM78M680 is equipped with a compound device, such as the receiver box controller for a wireless keyboard paired with a wireless mouse. pattern detect application (pda) can calculate the length of one pattern and interrupt the mcu while the serial signal is transiting from high to low (or vise-versa). then the mcu reads the length value from a specified register. 6.9.2 control register the pda includes two enable control bits, one control register and four length counter registers in 0x15 ~0x18 in extraram1. 6.9.2.1 iocf [2~3] pda enable control bit when this bit is set, the pda function starts and the p92 and p93 become input pin automatically to sample the serial signal.(note: enabling these two bits also enabling the interrupt mask of pda.) 0 : disable pda function 1 : enable pda function 6.9.2.2 ioca (pda control register) default value: (0b_0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rf.2 rf.1 rf.0 db2 db1 db0 this register is used to define two parameters of pda function; signal sampling rate and debounce length. when a pattern ends, the value in the counter is loaded into its respective register and the re[0~4] is set to indicate which channel and which type of pattern (high or low) is at its end or which type of pattern counter is on overflow. 0 : low pattern 1 : high pattern 6.9.2.3 r15 extraram1 (p.92 low pattern counter) this register records the length of p.92 in low status. contents product specification (v1.11) 02.10.2007 ? 27 6.9.2.4 r16 extraram1 (p.92 high pattern counter) this register records the length of p.92 in high status. 6.9.2.5 r17 extraram1 (p.93 low pattern counter) this register records the length of p.93 in low status 6.9.2.6 r18 extraram1 (p.93 high pattern counter) this register records the length of p.93 in high status. r15~r18 function as general registers if this function is not enabled. once the enabled bit is set, these four registers w ill be loaded with the value of the pattern counter. 6.9.3 sampling rate and debounce length the two pattern detect pins are separate, and each pin has its own pattern counter. both pins use the same sampling rate and debounce length parameters. the pda samples the serial signal for every fixed interval. the pattern counter will be incremented by one at sampling time if the signal remains unchanged. if the signal is at high state, then the ?high pattern counter? will be incremented, otherwise the ?low pattern counter? is incremented. as long as the signal state changes, the pda will debounce signal and load the value of the pattern counter into the respective register for the firmware to read. for example, if the signal in p.92 is in ?low? state, the low counter of p.92 will count continuously until the state of the input signal in p.92 changes. when a state change occurs (in this case, the signal changes from ?low? to ?high? state), the pda will take a time break (which is equal to the result of sampling interval multiplied by the debounce length), to avoid possible noise. after the debounce length time, if the signal remains in high state, the high pattern counter will start to count and load the low pattern counter?s value into r15 extraram1. at the same time, re [0] is set to indicate that the low pattern is over. the correlation between the value of control register and debounce time are as follows: db.2 db.1 db.0 debounce time 0 0 0 no sampling clock . 0 0 1 1 sampling clock 0 1 0 2 sampling clock 0 1 1 3 sampling clock . 1 0 0 4 sampling clock 1 0 1 5 sampling clock 1 1 0 6 sampling clock 1 1 1 7 sampling clock contents ? product specification (v1.11) 02.10.2007 28 now consider another situation of this case, where the signal of p92 always stays ?low?. the low pattern counter of p92 will eventually overflow. once the counter overflows, the content of the counter will also be loaded into r15, that is, the register is written to 0xff, then the counter is reset to count from zero again. if the hardware interrupt of pda function is enabled, (iocf[2] is equal to ?1?), then the program will go to 0x0010 to execute interrupt routine while the content of a pattern counter is loaded into the register. the correlation between the value of control register and actual sampling rate are as shown below: rf2 rf1 rf0 timing rate 8mhz system clock (time(cnt.)) 256khz rc mode (time (cnt.)) 0 0 0 1:1 0.125s (1), 31.875s (255) 3.91s (1), 996.1s (255) 0 0 1 1:2 0.25s (1), 63.75s (255) 7.81s (1), 1992s (255) 0 1 0 1:4 0.5s (1), 127.5s (255) 15.625s (1), 3984s (255) 0 1 1 1:8 1s (1), 255s (255) 31.25s (1), 7969s (255) 1 0 0 1:16 2s (1), 510s (255) 62.5s (1), 15.938ms (255) 1 0 1 1:32 4s (1), 1020s (255) 125s (1), 31.875ms (255) 1 1 0 1:64 8s (1), 2040s (255) 250s (1), 63.75ms (255) 1 1 1 1:128 16s (1), 4080s (255) 500s (1), 127.5ms (255) user can write a default value to the high pattern counter register and low pattern counter register. then set the corresponding interrupt enable bit (iocf [2, 3]). when the counting value of one ?h? patter n is bigger than the default value of r15_extraram1, a pattern detecting interrupt will be generated. similarly, if the counting value of one ?l? pattern is bigger than the default value of r16_extraram1, a low pattern detecting interrupt will occur. thus, the EM78M680 is notified and aware that one effective pattern is received from p.92. 6.10 pulse width modulation (pwm) 6.10.1 function description in pwm mode, both of pwm1 (p.92) and pwm2 (p.93) produce plus programmable signal of up to 8 bits resolution. the pwm period is defined as 0xff timer counter clock . the timer counter clock source is controlled by u i f control register iocb. for example; if the clock source is 1mhz, then the period will be 255s. period = 255 (1/timer counter clock) contents product specification (v1.11) 02.10.2007 ? 29 period (0xff * clock) duty cycle fig. 7-1 pwm output timing diagram 6.10.2 duty cycle the pwm duty cycle is defined by writing to the r15/r16 register of extraram0 for pwm1/ pwm2. duty cycle = ( r15 of extraram0/ 255 ) 100% for pwm1 ( r16 of extraram0/ 255 ) 100% for pwm2 6.10.3 control register 6.10.3.1 r15 of extra ram0(pwm1 duty cycle register) a specified value keeps the output of pwm1 to remain at high for a period of time. 6.10.3.2 r16 of extra ram0 (pwm2 duty cycle register) a specified value keeps the output of pwm2 to remain at high for a period of time. 6.10.3.3 iocb(pwm control register) default value: (0b_0000_0001) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw2_e pw1_e ? ? ? pwm_sr2 pwm_sr1 pwm_sr0 iocb [0~2] pwm clock prescaler base on mcu frequency (ex : fosc = 8mhz) pwm_sr2 pwm_sr1 pwm_sr0 clock(hz) period / 255 0 0 0 fosc / 2 0.25s 0 0 1 fosc / 4 0.5s 0 1 0 fosc / 8 1s 0 1 1 fosc / 16 2s 1 0 0 fosc / 32 4s 1 0 1 fosc / 64 8s 1 1 0 fosc / 128 16s 1 1 1 fosc / 256 32s iocb [6, 7] pwm1/pwm2 enable bit ? 0 ? : disable ? 1 ? : enable contents ? product specification (v1.11) 02.10.2007 30 6.11 analog-to-digital converter (adc) 6.11.1 function description the analog to digital converter consists of a 5-bit analog multiplexer, one control register (r11_extraram0), and two data registers (r13_extraram0 ~ r14_extraram0) for a 10-bit resolution. the adc module utilizes successive approximation to convert the unknown analog signal to a digital value. the result is fed to the addata. input channels are selected by the analog input multiplexer via the adcr/ad_sel bits ad0~ad4. ? 10-bit resolution: 0x00-00~0xc0-ff (0b11000000-11111111) ? start (0x00-00): 0 vref~(1/1024)*vref ? full (0xc0-ff): (1023/1024)*vref~vref ? conversion time: 12 clock time of internal clock source 6.11.2 control register 6.11.2.1 r11 (ad channel select register) default value: (0b_0001_1111) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ad_start ad_r1 ad_r0 ad4 ad3 ad2 ad1 ad0 r11 [0~4]: ad channel selector ad4 ad3 ad2 ad1 ad0 channel i/o port 0 0 0 0 0 0 p50 0 0 0 0 1 1 p51 0 0 0 1 0 2 p52 0 0 0 1 1 3 p53 0 0 1 0 0 4 p54 0 0 1 0 1 5 p55 0 0 1 1 0 6 p56 0 0 1 1 1 7 p57 0 1 0 0 0 8 p80 0 1 0 0 1 9 p81 0 1 0 1 0 10 p82 0 1 0 1 1 11 p83 0 1 1 0 0 12 p84 0 1 1 0 1 13 p85 0 1 1 1 0 14 p86 0 1 1 1 1 15 p87 1 0 0 0 0 16 p60 1 0 0 0 1 17 p61 1 0 0 1 0 18 p62 1 0 0 1 1 19 p63 1 0 1 0 0 20 p64 1 0 1 0 1 21 p65 1 0 1 1 0 22 p66 1 0 1 1 1 23 p67 contents product specification (v1.11) 02.10.2007 ? 31 r11 [5 6]:the clock source of ad converting. 00 : 256khz 01 : 128khz 10 : 64khz 11 : 32khz r11 [7] ad converter start flag 0 ? 1 : start ad conversion (set by firmware) 1 ? 0 : when ad finishes converting and has moved the digital data into the ad data register, this bit will be reset by hardware. note hardware can enable this function only at ad channel selector of the functional i/o port . after power-on reset, the initial value of this register is 0b0001 1111 . 6.11.2.2 r13 (ad lsb data register) default value: (0b_0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 0 0 0 0 0 0 ad digital data lsb 2 bits 6.11.2.3 r14 (ad msb data register) default value: (0b_0000_0000) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 ad digital data msb 8 bits 7 absolute maximum ratings items min max unit temperature under bias 0 70 oc storage temperature -65 150 oc input voltage -0.5 6.0 v output voltage -0.5 6.0 v contents ? product specification (v1.11) 02.10.2007 32 8 dc electrical characteristic ta=25 c, vdd=5v, vss=0v symbol parameter condition min typ max unit vdd operating voltage ? 4.4 5.0 5.25 v iil input leakage current vin = vdd, vss ? ? 1 a vih input high voltage ? 2.0 ? ? v vil input low voltage ? ? ? 0.8 v vihx clock input high voltage osci 2.5 ? ? v vilx clock input low voltage osci ? ? 1.0 v voh1 output high voltage (p70~p72, p76~p77) ioh = 7.0ma vdd = 5 v 2.4 ? ? v voh2 output high voltage (ports 5, 6, 8, p90~p93, p95~p96) ioh = 7.0ma vreg = 3.3 v 2.4 ? ? v vol1 output low voltage (p70~p72, p76~77) iol = -8.0ma vdd = 5 v ? ? 0.4 v vol2 output low voltage (p70~p72 : led drive mode) iol = -8.0ma vdd = 5 v ? ? 3.0 v vol3 output low voltage (ports 5,6,8, p90~p93, p95~p96) iol = -8.0ma vreg = 3.3 v ? ? 0.4 v iph1 pull-high current (ports 5, 6, 7, 8, p90~p93, p95~p96) pull-high active, input pin at vss vreg=3.3v -20% 132 +20% a iph2 pull-high current (p70~p72, p76~77) pull-high active, input pin at vss vdd = 5 v -20% 132 +20% a iph3 pull-high current (usb d+) pull-high active, input pin at vss vreg=3.3v ? 2.2 ? ma icc1 operating supply current normal operation fosc= 8mhz , no gpio loading ? ? 10 ma icc2 operating supply current sleep mode all input and i/o pin at vdd, output pin floating, wdt disabled ? ? 100 a icc3 operating supply current dual clock mode ? 256khz all input and i/o pin at vdd, output pin floating, wdt disabled ? ? 250 a contents product specification (v1.11) 02.10.2007 ? 33 vreg output voltage of 3.3v regula tor vdd = 4.4v ~ 5.25v 3.0 3.3 3.6 v contents ? product specification (v1.11) 02.10.2007 34 appendix a special register map address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name c57 c56 c55 c54 c53 c52 c51 c50 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a ioc5 wake-up from pin change p p p p p p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a ioc6 wake-up from pin change p p p p p p p p bit name c77 c76 - - - c72 c71 c70 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a ioc7 wake-up from pin change p p p p p p p p bit name c87 c86 c85 c84 c83 c82 c81 c80 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a ioc8 wake-up from pin change p p p p p p p p bit name c97 c96 c95 c94 c93 c92 c91 c90 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a ioc9 wake-up from pin change p p p p p p p p bit name - - rf2 rf1 rf0 rf_db2 rf_db1 rf_db0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0a ioca (rfcnt) wake-up from pin change p p p p p p p p bit name pw2_e pw1_e - - - pwm_2 pwm_1 pwm_0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0b iocb (pwm_cnt) wake-up from pin change p p p p p p p p contents product specification (v1.11) 02.10.2007 ? 35 address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name gpb gpb gpb gpb gpb - - - power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0c iocc (do not use) wake-up from pin change p p p p p p p p bit name - /ph96 /ph95 - /ph93 /ph92 /ph91 /ph90 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x0d iocd (p9_ph) wake-up from pin change p p p p p p p p bit name s7 /wue wte slpc - /pu8 /pu6 /pu5 power-on 1 1 0 1 u 1 1 1 /reset and wdt 1 1 0 1 u 1 1 1 0x0e ioce (mcu cnt) wake-up from pin change p p p 1 u p p p bit name outep p7ie -- resuie rf2ie rf1ie usbie tcie power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0f iocf wake-up from pin change p p p p p p p p bit name - int tsr2 tsr1 tsr0 psr2 psr1 psr0 power-on u 0 1 1 1 1 1 1 /reset and wdt u p 1 1 1 1 1 1 n/a cont wake-up from pin change u p p p p p p p bit name - - - - - - - - power-on u u u u u u u u /reset and wdt p p p p p p p p 0x00 r0(iar) wake-up from pin change p p p p p p p p bit name - - - - - - - - power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x01 r1(tcc) wake-up from pin change p p p p p p p p bit name - - - - - - - - power-on 0 0 0 0 0 0 0 0 0x02 r2(pc) /reset and wdt 0 0 0 0 0 0 0 0 contents ? product specification (v1.11) 02.10.2007 36 address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wake-up from pin change ** p ** p ** p ** p ** p ** p ** p ** p bit name ps2 ps1 ps0 t p z dc c power-on 0 0 0 t t u u u /reset and wdt 0 0 0 t t p p p 0x03 r3 (sr) wake-up from pin change p p p t t p p p bit name rsr.1 rsr.0 - - - - - - power-on 0 0 u u u u u u /reset and wdt 0 0 p p p p p p 0x04 r4 (rsr) wake-up from pin change p p p p p p p p bit name p57 p56 p55 p54 p53 p52 p51 p50 power-on u u u u u u u u /reset and wdt p p p p p p p p 0x05 r5 (p5) wake-up from pin change p p p p p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 power-on u u u u u u u u /reset and wdt p p p p p p p p 0x06 r6 (p6) wake-up from pin change p p p p p p p p bit name p77 p76 - - - p72 p71 p70 power-on u u u u u u u u /reset and wdt p p p p p p p p 0x07 r7 (p7) wake-up from pin change p p p p p p p p bit name p87 p86 p85 p84 p83 p82 p81 p80 power-on u u u u u u u u /reset and wdt p p p p p p p p 0x08 r8 (p8) wake-up from pin change p p p p p p p p bit name p97 p96 p95 p94 p93 p92 p91 p90 power-on u u u u u u u u /reset and wdt p p p p p p p p 0x09 r9 (p9) wake-up from pin change p p p p p p p p bit name ext_r remote ep0_w ep0_r d_resu udc_su udc_w stall power-on 0 0 0 0 0 0 0 0 0x0a ra(usbes) /reset and wdt 0 0 0 0 0 0 0 0 contents product specification (v1.11) 02.10.2007 ? 37 address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wake-up from pin change p p p p p p p p bit name gpb gpb gpb gpb gpb gpb gpb gpb power-on u u u u u u u u /reset and wdt p p p p p p p p 0x0b gpr wake-up from pin change p p p p p p p p bit name index7 index6 index5 index4 index3 index2 index1 index0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0c rc (fifo_index) wake-up from pin change p p p p p p p p bit name fifo7 fifo6 fifo5 fifo4 fifo3 fifo2 fifo1 fifo0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0d rd (fifo_data) wake-up from pin change p p p p p p p p bit name p77_if p76_if - - rf2_h rf2_l rf1_h rf1_l power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0e re (isr0) wake-up from pin change p p p p p p p p bit name out_ep gpb gpb resumif usbres suspend ep0_if tccif power-on 0 u u 0 0 0 0 0 /reset and wdt 0 p p 0 0 0 0 0 0x0f rf (isr0) wake-up from pin change p p p p p p p p bit name gpb gpb gpb ep5_st ep4_st ep3_st ep2_st ep1_st power-on u u u 0 0 0 0 0 /reset and wdt p p p 0 0 0 0 0 0x10 r10 (usb ep stat) wake-up from pin change p p p p p p p p bit name adstart ad_r1 ad_r0 ad4 ad3 ad2 ad1 ad0 power-on 0 0 0 1 1 1 1 1 /reset and wdt 0 0 0 1 1 1 1 1 0x11 r11 (ad/control) wake-up from pin change p p p p p p p p bit name gpb usb_to low_f1 low_f0 /lowfre gpb gpb gpb power-on u u 0 0 1 u u u 0x12 r12 (dual) /reset and wdt p u 0 0 1 p p p contents ? product specification (v1.11) 02.10.2007 38 address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wake-up from pin change p p p p p p p p bit name add1 add0 - - - - - - power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x13 r13 (adlodata) wake-up from pin change p p p p p p p p bit name add9 add8 add7 add6 add5 add4 add3 add2 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x14 r14 (adhidata) wake-up from pin change p p p p p p p p bit name pwm17 pwm16 pwm15 pwm14 pwm13 pwm12 pwm11 pwm10 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x15 r15 (pwm1_t) wake-up from pin change p p p p p p p p bit name pwm27 pwm26 pwm25 pwm24 pwm23 pwm22 pwm21 pwm20 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x16 r16 (pwm2_t) wake-up from pin change p p p p p p p p bit name gpb ee_act ee_rest eea4 eea3 ee_ok ee_c1 ee_c0 power-on u 0 0 0 0 1 1 1 /reset and wdt p 0 0 0 0 0 1 1 0x17 r17 (eecnt) wake-up from pin change p p p p p p p p bit name - - - - - - - - power-on u u u u u u u u /reset and wdt p p p p p p p p 0x18~0x3f gpr wake-up from pin change p p p p p p p p bit name -- -- -- -- -- -- -- -- power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x10 r10 (do not use) wake-up from pin change p p p p p p p p bit name gpb -- -- -- -- gpb gpb gpb power-on u 0 0 0 0 u u u 0x11 r11 (do not use) /reset and wdt p p p p p p p p contents product specification (v1.11) 02.10.2007 ? 39 address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wake-up from pin change p p p p p p p p contents ? product specification (v1.11) 02.10.2007 40 address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name -- -- -- -- -- -- -- -- power-on 0 0 0 u 0 0 u 0 /reset and wdt 0 0 0 p 0 0 p 0 0x12 r12 (do not use) wake-up from pin change p p p p p p p p bit name -- -- -- -- gpb -- -- -- power-on 0 0 0 0 u 0 0 0 /reset and wdt 0 0 0 0 p 0 0 0 0x13 r13 (do not use) wake-up from pin change p p p p p p p p bit name -- -- -- -- -- -- -- -- power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x14 r14 (do not use) wake-up from pin change p p p p p p p p bit name se1_l7 se1_l6 se1_l5 se1_l4 se1_l3 se1_l2 se1_l1 se1_l0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x15 r15 (se1_low) wake-up from pin change p p p p p p p p bit name se1_h7 se1_h6 se1_h5 se1_h4 se1_h3 se1_h2 se1_h1 se1_h0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x16 r16 (se1_high) wake-up from pin change p p p p p p p p bit name se2_l7 se2_l6 se2_l5 se2_l4 se2_l3 se2_l2 se2_l1 se2_l0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x17 r17 (se2_low) wake-up from pin change p p p p p p p p bit name se2_h7 se2_h6 se2_h5 se2_h4 se2_h3 se2_h2 se2_h1 se2_h0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x18 r18 (se2_high) wake-up from pin change p p p p p p p p bit name - - - - - - - - power-on u u u u u u u u /reset and wdt p p p p p p p p 0x19~0x3f gpr wake-up from pin change p p p p p p p p ** execute the next instruction after the ?slpc? bit status of ioce register has been on high-to-low transition . x: not for use. u: unknown or don?t care. p: previous value before reset. contents product specification (v1.11) 02.10.2007 ? 41 b instruction set each instruction in the instruction set is a 13-bit word divided into an op code and one or more operands. all instructions are executed within one single instruction cycle (consisting of 2 oscillator periods), unless the program counter is changed by- (a) executing the instruction "mov r2,a", "add r2,a", "tbl", or any other instructions that write to r2 (e.g. "sub r2,a", "bs r2,6", "clr r2", ???? ). (b) execute call, ret, reti, retl, jmp, conditional skip (jbs, jbc, jz, jza, djz, djza) which were tested to be true. under these cases, the execution takes two instruction cycles. in addition, the instruction set has the following features: (1). every bit of any register can be set, cleared, or tested directly. (2). the i/o register can be regarded as general register. that is, the same instruction can operate on i/o register. legend: r = register designator that specifies which on e of the 64 registers (i ncluding operation and general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. b = bit field designator that selects the value for th e bit located in the regi ster r and which affects the operation. k = 8 or 10-bit constant or literal value binary instruction hex mnemonic operation status affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a cont none 0 0000 0000 0011 0003 slep 0 wdt, stop oscillator t, p 0 0000 0000 0100 0004 wdtc 0 wdt t, p 0 0000 0000 rrrr 000r iow r a iocr none contents ? product specification (v1.11) 02.10.2007 42 binary instruction hex mnemonic operation status affected 0 0001 00rr rrrr 01rr sub a,r r-a a z, c, dc 0 0001 01rr rrrr 01rr sub r,a r-a r z, c, dc 0 0001 10rr rrrr 01rr deca r r-1 a z 0 0001 11rr rrrr 01rr dec r r-1 r z 0 0010 00rr rrrr 02rr or a,r a vr a z 0 0010 01rr rrrr 02rr or r,a a vr r z 0 0010 10rr rrrr 02rr and a,r a & r a z 0 0010 11rr rrrr 02rr and r,a a & r r z 0 0011 00rr rrrr 03rr xor a,r a r a z 0 0011 01rr rrrr 03rr xor r,a a r r z 0 0011 10rr rrrr 03rr add a,r a + r a z, c, dc 0 0011 11rr rrrr 03rr add r,a a + r r z, c, dc 0 0100 00rr rrrr 04rr mov a,r r a z 0 0100 01rr rrrr 04rr mov r,r r r z 0 0100 10rr rrrr 04rr coma r /r a z 0 0100 11rr rrrr 04rr com r /r r z 0 0101 00rr rrrr 05rr inca r r+1 a z 0 0101 01rr rrrr 05rr inc r r+1 r z 0 0101 10rr rrrr 05rr djza r r-1 a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) a(n-1), r(0) c, c a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) r(n-1), r(0) c, c r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) a(n+1), r(7) c, c a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) r(n+1), r(7) c, c r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) a(4-7), r(4-7) a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 r(b) none contents product specification (v1.11) 02.10.2007 ? 43 binary instruction hex mnemonic operation status affected 1 1111 kkkk kkkk 1fkk add a,k k+a a z, c, dc note: 1 this instruction is applicable to iocx only. 2 this instruction is not recommended for re, rf operation. contents ? product specification (v1.11) 02.10.2007 44 c code option bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 /protect usb /d+ resistor ost0 ost1 frq0 frq1 pkg0 pkg1 reversed /ad hold bit 11 bit 12 bit 13~15 bit 16~17 bit 18 bit 19~20 bit 22~22 bit 23 reserved reserved epx_sel ep1 type ep1 direction ep1 max size ep2 type ep2 direction bit 24~25 bit 26~27 bit 28 bit 29~30 bit 31~32 bit 33 bit 34~35 ep2 max size ep3 type ep3 direction ep3 max size ep4 type ep4 direction ep4 max size bit 36~37 bit 38 bit 39~40 bit 41~42 bit 43~59 bit 60~63 ep5 type ep5 direction ep5 max size reserved user id reserved bit 0 (/protect): protect bit. 1 : disable 0 : enable. bit 1 (usb): operation mode. 1 : usb mode 0 : non-usb mode. close udc & transceiver function. bit 2 (/d+ resistor): d+ resistor pull-high switch. 1 : disable internal usb d+ pull-high resistor. 0 : enable internal usb d+ pull-high resistor. bit 4~3 (ost1~ost0): oscillator start time. wdt time-out time. 00 : 500 s 01 : 2 ms 10 : 4 ms 11 : 8 ms bit 6~5 (frq1~frq0): system clock frequency switch. 00 : 8mhz, external crystal 2 01 : 16mhz, external crystal 4 10 : 24mhz, external crystal 6 11 : not defined contents product specification (v1.11) 02.10.2007 ? 45 bits 8~7 (pkg1~pkg0): package switch. 00 : 20 pins 01 : 24 pins 10 : 40 pins 11 : 44 pins bit 9 (reverse): set? 0? as default value bit 10 (/adhold): setting mcu when ad converting 0 : hold mcu when ad converting. 1 : keep mcu running when ad converting. bit 11 ~ bit 12 : reserved reserve, set as ?0, 0? bits 15 ~ 13 (epx_sel2 ~ epx_sel0): endpoint function selection epx status / epx fifo max size epx_sel[2 : 0] (usb mode) ep1 ep2 ep3 ep4 ep5 000 enable / 64 bit disable / na disable / na disable / na disable / na 001 enable / 64 bit enable / 64 bit disable / na disable / na disable / na 010 enable / 64 bit enable / 32 bit enable / 32 bit disable / na disable / na 011 enable / 64 bit enable / 32 bit enable / 16 bit enable / 16 bit disable / na 100 enable / 64 bit enable / 32 bit enable / 16 bit enable / 8 bit enable / 8 bit 101 enable / 64 bit enable / 16 bit enable / 16 bit enable / 16 bit enable / 16 bit 110 enable / 32 bit enable / 32 bit enable / 32 bit enable / 32 bit disable / na 111 enable / 32 bit enable / 32 bit enable / 32 bit enable / 16 bit enable / 16 bit bits 16 ~ 40 : epx type : 00 not defined 01 isochronous mode transfer 10 bulk mode transfer 11 interrupt mode transfer epx direction : 0 output way 1 input way contents ? product specification (v1.11) 02.10.2007 46 epx max size : 00 8 bytes 01 16 bytes 10 32 bytes 11 64 bytes if epx max size selection is larger than endpoint function selection, epx fifo size will depend on the size of endpoint function selector (epx_sel0~2]). bits 41 ~ 42 (reserved): reserved bit default : 1 bits 43~ bit 59 (user id): define by user. bits 60~63 (reserved): reserved bit EM78M680 usb full speed microcontroller product specification (v1.1) 02.10.2007 ? (this specification is subject to change without further notice) 47 d. application circuit : |
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